01
Format a microSD card.
One FAT32 partition with an MBR partition table, not exFAT, which cards over 32 GB get by default. Any volume name will do.
muir-fpga · QUUX and the CADR in FPGA fabric
QUUX and the CADR,
in FPGA fabric.
What runs on each of the boards.
Every part of it is held to muir-sim, a simulator of the same machines, tick for tick. The CADR runs within about 5% of MIT’s speed (why). QUUX runs as a pipeline of four stages, a clock a stage, at the period each board’s fit closes at, which the boards’ table gives.
QUUX ON THE KRIA KR260MUIR-FPGA
![QUUX’s screen on the Kria KR260 after a cold boot: [Loading error table for microcode version 2002]; MIT System, band 1 of LOCALHOST.; 32768K physical memory, 163634K virtual memory.; Experimental System 2002; Microcode 2002; Machine Type QUUX on Kria KR260; MIT localhost, with associated machine FILES.; ;Reading at top level in Lisp Listener 1.; ;Reading in base 10 in package USER with standard traditional syntax readtable.](kr260-herald.png)
01 / WHAT IT IS
QUUX and the CADR
in the fabric.
muir-fpga puts QUUX and the CADR in the fabric of an FPGA. The CADR is the Lisp Machine MIT designed around 1978, and muir-fpga’s CADR is muir-sim’s RTL model of it, synthesized into the fabric of an FPGA — the two processor boards, the bus interface, the disk controller, the display and the I/O board.
The same fabric is built as QUUX too, the CADR evolved; the boards’ table says which board runs which. Each machine boots its own muir-sys system, and the CADR gets its files and the time from ozd.
02 / THE BOARDS
The boards,
and what each runs.
Every board has Ethernet and a microSD card, so the table leaves them out. A bar is the share of the chip’s logic and block memory that a machine uses; under QUUX’s, the period of its clock and its cache on that board.
| Board | CADR | QUUX | Display | USB input |
|---|---|---|---|---|
| Arty Z7-20AMD Zynq 7020XC7Z020made by Digilent | LUTs15,187 / 53,200 LUTs BRAM46 / 140 block RAM tiles |
LUTs28,415 / 53,200 LUTs BRAM96 / 140 block RAM tiles 16.7 MHz (60 ns clock)4K words cache |
HDMI1280×102460 Hz | Keyboard Mouse |
| Kria KR260AMD Zynq UltraScale+ K26XCK26made by AMD | LUTs15,309 / 117,120 LUTs BRAM41 / 144 block RAM tiles URAM0 / 64 UltraRAM blocks |
LUTs31,767 / 117,120 LUTs BRAM43.5 / 144 block RAM tiles URAM14 / 64 UltraRAM blocks 40 MHz (25 ns clock)64K words cache |
DisplayPort1920×108060 Hz | Keyboard Mouse |
| DE25-NanoAltera Agilex 5 E-seriesA5EB013Bmade by Terasic | ALMs18,108 / 46,800 ALMs M20K135 / 358 M20K blocks |
ALMs35,496 / 46,800 ALMs M20K162 / 358 M20K blocks 40 MHz (25 ns clock)16K words cache |
HDMI1280×102460 Hz | Keyboard Mouse |
03 / USING IT
From a card
to a prompt.
Ready-made files for a microSD card, a zip for each board and machine. Nothing has to be built.
| Board | CADR | QUUX |
|---|---|---|
| Arty Z7-20 | cadr-arty-z7-20.zip | quux-arty-z7-20.zip |
| Kria KR260 | cadr-kria-kr260.zip | quux-kria-kr260.zip |
| DE25-Nano | cadr-de25-nano.zip | quux-de25-nano.zip |
The CADR, from muir-sys’s latest-cadr:
cadr-pack.img.gz, uncompressed and copied to the card aspacks/disk-pack-0.img.cadr-sys.tar.gz, unpacked; itssysandsitefolders go onto the card’ssys/andsite/.
QUUX, from muir-sys’s latest-quux:
quux-disk.vhd.gz, uncompressed and copied to the card aspacks/disk-pack-0.img.quux-sys.tar.gz, unpacked; itssysandsitefolders go onto the card’ssys/andsite/.
02
Unzip the zip onto it.
Your board’s zip, onto the root of the card. A zip works only on the board it is named for.
03
Add the system.
The disk as packs/disk-pack-0.img, and the sys and site folders as sys/ and site/, from the downloads above. The README.TXT in each zip names the System its card is for, with the muir-sys release and the files. Both boot with an empty sys/, on the band’s own error table; loading or compiling a file of the system needs its sys and site folders on the card. The machine reads and writes sys/ and site/, so a file it compiles is written beside its source, and a tree it damages is put back from the system’s sources tarball.
04
Set the date.
The boards keep no time while switched off. With a network, a board sets its clock by NTP at boot, from pool.ntp.org, before the machine starts; --ntp-server in fpgarc names another server and --no-ntp turns it off. Without a network, open fpgarc on the card and replace the two lines #--date yyyyMMdd and #--time HHmm with today’s date and the time in UTC, for example --date 20261002 and --time 1430. With neither, the machine starts in 1970.
05
Connect a screen and input.
A monitor and a USB keyboard and mouse (HDMI on the Arty Z7-20 and the DE25-Nano, DisplayPort, J6, on the Kria KR260), or Ethernet to a network with DHCP and a VNC viewer on port 5900 of the board’s address. On the Kria KR260 the network port is J10C, and its USB ports are for the keyboard and the mouse, with no other USB storage plugged in. On the Arty Z7-20 and the DE25-Nano the address can change from one boot to the next, so look for it in your router’s list.
06
Switch the board on.
Linux starts, and the machine boots from its disk by itself in about two minutes. The first time the machine reads a file it asks you to log in: log in as lispm, the name whose home directory the card provides.
The CADR’s card makes it LISPM-1, at Chaosnet address 177201; the release notes give its site’s other machines. The CADR has 32 memory boards by default; --main-memory-boards in fpgarc says another count from 1 to 60, and System 1003 and later use more; an older system halts at its cold boot with more than 32. On a QUUX card, main memory is 32MW by default; --main-memory-size in fpgarc says another amount in MW, from 1MW to the board’s most: 32MW on the Arty Z7-20, 32MW on the Kria KR260, 64MW on the DE25-Nano. The release page lists the digests of the zips, and each of muir-sys’s releases has a SHA256SUMS beside its files.
04 / WHOSE WORK, UNDER WHAT TERMS
License and
third-party material.
| What | Whose, and the terms | Where the terms are recorded |
|---|---|---|
| The work in this repository: the fabric, the checks and their reference traces, the programs beside the machine and the documents | This project’s. GNU Affero General Public License, version 3 or later | LICENSE, and the SPDX identifier AGPL-3.0-or-later in almost every file’s header |
Four files, for the Arty Z7-20: ps7_init_gpl.c, U-Boot’s default environment, the board’s device tree and the -u-boot.dtsi beside it | This project’s, under the GNU General Public License, version 2 or later, because each is compiled into U-Boot | each file’s own header |
| Digilent’s pin files | Digilent’s, under the MIT License | the Arty Z7-20’s constraint file cites the commit and digest of its pins |
| muir-sim | Its own repository, under the AGPL, version 3 or later | not carried; pinned by commit in muir.commit |
| Buildroot 2026.02.3, U-Boot 2026.01, Linux 6.19.14 | Each under its own license; for the loader and the kernel, the GPL, version 2 | not in the repository; the build fetches them |
| MIT’s own files: the schematics, wire lists, print sets and PROM images of 1977 to 1981, and the system software beside them | MIT’s. No statement of terms came with the engineering files and none is made up for them; the system release states the AGPL, version 3 or later | not in the repository; muir-sim carries them, recovered from the ITS backup tapes and unmodified |
05 / ABOUT
MIT’s machine, and
what muir-fpga adds.
The CADR, the schematics, the wire lists and the microcode are MIT’s, recovered by other people’s work over decades, and the machine in the fabric is held tick for tick to muir-sim; the documents list every source the drawings were read from and what each one is. The fabric, its checks and their reference traces, the programs beside the machine on the board and the documents are this project’s.
muir-fpga is written with Claude Code, using Anthropic’s Claude Opus, Claude Fable and Claude Sonnet. The machine is written in SystemVerilog, its testbenches in C++ for Verilator, the programs beside it on the board in C, and the generators of its reference traces in Rust.
muir-fpga is muir-sim’s RTL model of the CADR and of QUUX, synthesized into the fabric of an FPGA and held to muir-sim tick for tick.
© 2026 Mete Balci. muir-fpga is AGPL-3.0-or-later. MIT’s own files are not in this repository: muir-sim carries them, unmodified.