muir↗CADR PRESERVED.
QUUX EVOLVED.

muir-fpga · Digilent · Zynq 7020

Arty Z7-20

QUUX and the CADR mapped onto one AMD Zynq 7020, the XC7Z020.

The processing system: 2 × Arm Cortex-A9, running Linux.

The CADR’s drawingQUUX’s drawingHow it bootsThe debug cableKria KR260DE25-NanoThe maker’s page ↗
FIG. 01 — ARTY Z7-20, CADRMUIR-FPGA
this project another project board component AMD Zynq 7020 · XC7Z020-1CLG400C display output scans both screens out of DDR at the monitor’s rate, side by side, the color one over the first; TMDS to HDMI S_AXI_HP3 FPGA masters, 64-bit HDMI out display out of the fabric, 1280 × 1024 at 60 Hz Programmable Logic LUTs 15,187 of 53,200 28.5% BRAM 207 KB of 630 KB 32.9% worst setup +0.275 ns clock CLOCK1, CLOCK2 100 MHz, 10 ns a tick 15 ticks=150 ns ICMEM board control store: 16K × 48, 768 Kb CADR board datapath, sequencer, scratchpads, maps 12 wires clock, SPY control, resets 80 wires MEM<31:0>, SPY<15:0> 48 driven from both ends bus interface BUSINT arbitration, the NXM timeout, the address decode, -HANG, its registers, the map, the cable debug cable adapter the cable both ways, 8 pins registers at GP1 + 0x1000 20 out 19 in Xbus, 32 bits Unibus, 16 bits, open collector Xbus to DDR main memory and the display’s buffer an AXI4 master disk controller four registers, the channel that walks a list in memory CADRDC an AXI4 master TV scan counters and the mode register SIMPLETV the buffer is in DDR Color TV second display board: 576 × 454 × 4 bits LISPMTV 0o17200000 I/O board keyboard, mouse, clocks, serial Chaosnet registers and buffers CADRIO the cable, not the protocol S_AXI_HP0 FPGA masters, 64-bit S_AXI_HP2 FPGA masters, 64-bit M_AXI_GP0 Arm masters, 32 bits, AXI3 M_AXI_GP1 Arm masters, 32-bit PS — Arm Linux — Buildroot 2 × Cortex-A9 650 MHz, Linux SPL U-Boot terminal an RFB server: the screen, the keys and the mouse Chaosnet routing, and the cable to the net for other machines serial serial line on a TCP socket, as muir-sim does disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over M_AXI_GP1 a Unibus master USB input the keyboard and mouse, onto the I/O board via the terminal muir-sim on Linux, running CC debugger ozd the files, the time and the host table DDR controller four ports, arbitrated in hardware MAC gigabit Ethernet SD host the card UART Linux’s console 512 MB DDR3 16 MB reserved for main memory, 1 MB for the display, 128 KB for disk packs — and Linux has the rest, 493,976 kB Pmod JA Debug cable 2 out + 2 in Vcc open both sides BTN0 — BOOT BTN1 — RESET LD0 — MACHRUN LD1 — fabric clock LD2 — microcycles LD3 — disk activity LD4 — ERRHALT LD5 — PROMENABLE SW0 — NO AUTO BOOT USB host keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; Chaosnet reaches other machines; the serial line is a TCP socket microSD U-Boot, CADR bitstream, Linux, root filesystem, disk packs, a file each USB-UART / JTAG micro-USB socket, console and JTAG
FIG. 02 — ARTY Z7-20, QUUXMUIR-FPGA
this project another project board component AMD Zynq 7020 · XC7Z020-1CLG400C display output scans the frame buffer out of DDR at the monitor’s rate; TMDS to HDMI S_AXI_HP3 FPGA masters, 64-bit HDMI out display out of the fabric, 1280 × 1024 at 60 Hz Programmable Logic LUTs 28,415 of 53,200 53.4% BRAM 432 KB of 630 KB 68.6% worst setup +0.930 ns clock quux15_arty 125 MHz in, MMCM, period 60 ns, a stage a clock processor 40-bit word, MUL and DIV, control store 16K words, PDL buffer 16K words the TLB 4,096 entries, a walk on a miss memory port a cycle goes to the memory bus, a device register or nowhere cache 4,096 words, two ways, write-through, lines of 8 words device cycles register page physical 1777777400-1777777777 the feature words, read only; the interrupt status, errors, three interval timers and the real-time clock console boot, halt, step, status the registers on GP1 device registers memory master lines of 8 words in five 64-bit beats quux15_axi_master an AXI4 master block-disk four registers, 200 to 203; blocks to and from a pack quux15_block_walk the pack side, a master video controller one-bit frame buffer, 1280 × 1024, a mode quux15_devices the buffer is in DDR file device two rings in main memory; registers quux15_devices its host face on GP0 keyboard and mouse a FIFO of 64 key words, the mouse’s counts, buttons quux15_input the cable, not the protocol Ethernet device two rings in main memory; registers quux16_ethernet its host face on GP0 S_AXI_HP0 FPGA masters, 64-bit S_AXI_HP2 FPGA masters, 64-bit M_AXI_GP0 Arm masters, 32 bits, AXI3 M_AXI_GP1 Arm masters, 32-bit PS — Arm Linux — Buildroot 2 × Cortex-A9 650 MHz, Linux SPL U-Boot Ethernet device frames between the rings and quux0, a host-only tap or a LAN tap terminal an RFB server: the screen, the keys and the mouse file device serves FILES and sets the clock, from the card disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over M_AXI_GP1 the registers USB input the keyboard and mouse, onto the register page via the terminal DDR controller four ports, arbitrated in hardware MAC gigabit Ethernet SD host the card UART Linux’s console 512 MB DDR3 QUUX’s areas: 32MW main memory, 1 MB display, 128 KB packs — and Linux has the rest, 350.875 MB BTN0 — unused BTN1 — RESET LD0 — running LD1 — fabric clock LD2 — microcycles LD3 — disk activity LD4 — ERRHALT LD5 — dark SW0 — unused USB host keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; a LAN tap puts QUUX on the LAN microSD U-Boot, the bitstream, Linux, root filesystem, disk packs, a file each USB-UART / JTAG micro-USB socket, console and JTAG