muir-fpga · questions
Questions
Questions this project is asked, each answered from the file that settles it.
Each answer here is a sentence or two. MIT’s own files are cited at the path muir-sim gives them, and the rest are files here.
01 / SIX QUESTIONS
The machine.
Why is there no disk multiplexor block?
MIT built one, board type LG684, and its work is electrical: it fans the controller’s one read and write path out to eight drives. Here a drive is a file on the card, so there is nothing for such a board to do, and the controller selects among eight units by DA<30:28> as MIT’s does.
Rests on MIT’s mit/cadrdc/dm.txt, dm.wls, dm.eco and disk.hand; muir-sim’s src/cable.rs and src/disk_controller.rs; docs/disk-controller.md.
Why is muir-sim the reference, and what does “held tick for tick” mean?
A machine with no reference is a machine nobody can check. Each file in rtl/machine/ is compared against a muir-sim type over a recorded trace, cycle for cycle, and muir.commit names the muir-sim the traces were taken from.
Rests on README.md; the header of mutations/list.txt.
Why is a tick ten nanoseconds?
Because the design does not meet its timing with a 5 ns clock. The CADR placed its clock edges with delay lines, and here each of MIT’s instants goes to the first 10 ns tick at or after it, so some edges fall up to 7 ns later, and the processor and its clocks run within about 5% of the original speed. muir-sim’s fpga timing model rounds the same way.
Rests on docs/timing.md; the header of rtl/machine/cadr_tick_pkg.sv; README.md.
Does the machine’s own clock agree with the wall?
Yes, while the grid and the tick are the same number: the microsecond clock counts 100 ticks, one real microsecond, and the vertical interrupt arrives at the rate of the sync program the board runs: 64.70 Hz from MIT’s PROM program until the band loads its own, and 60.503 Hz from CPT-SYNC2, which every boot loads.
Rests on docs/io-board.md, docs/tv.md, docs/board.md.
Is the color TV four bits a pixel or eight?
Four, and nothing here implements eight: a pixel is a four-bit address into a map of sixteen colors, each of three eight-bit channels.
Rests on docs/tv.md; muir-sim’s src/tv.rs; MIT’s sys/window/color.lisp, sys/ucadr/uc-hacks.lisp and cadrtv/lmtv.order.
Why does the screen keep the previous boot’s picture?
Because the real machine did: no reset clears the frame buffer, and MIT wrote the clear in software, which runs when the band comes up.
Rests on docs/tv.md; MIT’s sys/sys/ltop.lisp in the System 100 release.
02 / FIVE QUESTIONS
The boards, and the way
they are checked.
Why is the debug cable on one Pmod connector?
A board is a debugger or a debuggee and never both at once, and neither group of four pins is ever driven from both ends, so one connector carries the whole link both ways.
Rests on docs/debug-cable.md.
How does a board become the debugger?
With --debug-cable-connect in fpgarc at boot, or cadr-console debug-cable-connect at any time. With nothing said, a board is a debuggee.
Rests on docs/debug-cable.md.
Why are the checks themselves mutation-tested?
make check says the checks pass. make mutants says the checks can still fail.
Rests on docs/mutations.md.
Why is there no ILA or other Vivado debug core?
The free BASIC tier refuses create_debug_core, so the probe is a BSCANE2 and a shift register, which fills from reset and freezes with nobody at the board.
Rests on the header of rtl/plumbing/cadr_probe.sv; docs/toolchain.md.
What license is this under, and what in it is not this project’s work?
The GNU Affero General Public License, version 3 or later, apart from four files compiled into U-Boot under the GPL, version 2 or later. The third-party material is on the boards page.
Rests on docs/license.md.