THE MICROINSTRUCTIONTHE CONTROL STORE
64
bits, against 48
MIT’s 48 bits keep their meaning, and 16 more give the pipeline its predictions: a conditional jump’s hint, a dispatch’s predicted target, or a PDL address field.
THE MACHINES · QUUX, THE CADR EVOLVED
QUUX
QUUX is the CADR, evolved: MIT’s microinstruction and the same way of running Lisp, with the processor, its memory and its devices rebuilt where a change pays for itself.
muir-sim models it as quux, beside cadr, MIT’s machine as built; muir-fpga builds it for FPGA boards.
QUUX keeps the CADR’s microinstruction, inside a wider one of its own, and its way of running Lisp, and changes the parts that held it back. Three projects make it: muir-sim models each change and holds it to tests; muir-sys writes the microcode and builds the Lisp system for it; muir-fpga is the machine on an FPGA board, where --machine quux chooses it. The CADR stays MIT’s machine; QUUX runs muir-sys’s microcode and system for it, the 2xxx releases.
01 / CONTROL AND DATA PATHS
The processor.
FIG. 01 — THE PROCESSORQUUX
02 / THE MEMORY PORT AND THE REGISTER PAGE
The whole machine.
The CADR puts everything behind its bus interface: main memory, the disk and the display on the Xbus, and the keyboard, mouse, clocks and network on the Unibus through the I/O board.
QUUX’s processor has its microsecond clock inside, reaches main memory and the frame buffer on a port of its own through a cache, and its devices’ registers through its register decode, all of them on its register page; the devices move bulk data to and from memory themselves. There is no Unibus, no bus interface and no debug cable.
FIG. 02 — THE WHOLE MACHINEQUUX
03 / WHAT QUUX CHANGES
Rebuilt where
it pays.
QUUX names itself in a word only it answers, its MACHINE-ID, and lists its sizes on a page of device registers, its feature page. Software reads that word first, then the page.
THE PIPELINENO DELAY LINES
4
stages, one clock each
The CADR times a microcycle with delay lines. QUUX fetches, reads, executes and writes back in four stages of one clock each, predicting each transfer and checking it a clock later.
PAGINGA TLB
232
words of virtual address space, against 224
No map: a page table in main memory, which the hardware walks when its TLB misses. Virtual addresses are 32 bits, physical 28, and a page is 1024 words.
THE PDL BUFFERTHE STACK
16K
words, against 1K
It needs QUUX’s own boot PROM, and microcode that knows the size: MIT’s 323 does not run on it.
MULTIPLY AND DIVIDEONE INSTRUCTION EACH
5 and 18
clocks, multiply and divide, against 32 steps each
ALU functions 42 and 43, each bit for bit what the CADR’s step sequence gives.
CLOCKS OF ITS OWNTHE TIMERS
3
interval timers, and a microsecond clock in the processor
QUUX’s processor reads a microsecond clock in one microinstruction, and its register page has three interval timers. Timer 0 is the tick, the machine’s 60-cycle clock.
THE VIDEO CONTROLLERTHE DISPLAY
1920×1080
at most, one bit a pixel
A plain frame buffer and one register in place of the CADR’s TV boards. Each board’s bitstream fixes its size (the boards), and the system reads the size from the feature page at boot, so one band runs on each.
BLOCK-DISKTHE DISK
228
blocks, addressed by number
The CADR disk controller’s registers and command lists with the drive’s cylinders, heads and sectors taken out: numbered blocks of 1,024 bytes. It is QUUX’s only disk.
NO UNIBUSTHE I/O BOARD
0
Unibus cycles, and no I/O board
The keyboard and mouse and the interrupt and error status are on QUUX’s register page and the microsecond clock is in the processor. There is no serial port and no debug cable: the console’s registers are the host’s port alone.
THE MEMORY PORTTHE CACHE
4K–64K
words of cache, by board
Main memory is off the bus the CADR shares with its devices: the processor reaches it, and the frame buffer, on a port of its own through a two-way, write-through cache of 8-word lines. The CADR’s bus interface has nothing left to do, and QUUX has none.
DEVICE REGISTERSTHE REGISTER PAGE
1
page of device registers, and no bus
The processor reaches its devices’ registers through its own register decode, all of them on one register page at the end of the device window: the video controller’s, block-disk’s and the Ethernet device’s with the rest. Registers carry control and small data; bulk data moves between a device and memory by itself.
THE REAL-TIME CLOCKTHE TIME
1970
and whole seconds since, in one word
The real time as Unix seconds, an unsigned 32-bit number that lasts to 2106. It is live: the host keeps it, and the machine never sets it.
THE FILE DEVICEFILES
FILES
folders of the host, as one pathname host
QUUX reads and writes files on its host through a device of its own: commands and responses in two rings in main memory, the bytes moved by direct memory access, and the registers carrying control and the rings’ indexes.
THE ETHERNET DEVICETHE NETWORK
TCP
and IPv4, ARP and ICMP echo, in Lisp, in place of Chaosnet
The Ethernet device moves Ethernet frames by direct memory access and checks their checksums; ARP, IPv4, ICMP echo and TCP are written in Lisp, and the system’s TELNET server is reached over TCP. QUUX reaches its host through a tap, and the host’s LAN through a LAN tap, the host answering ARP for it.
A STANDARD DISKTHE DISK FILE
VHD
or a raw image, with a GPT partition table
QUUX’s disk is a raw image or a VHD, of any size, partitioned by GPT and made and filled with standard tools. The CADR keeps MIT’s pack and label.
THE FUSED RETURNTHE MAIN LOOP
1,024
entries of a MACRO DISPATCH MEMORY
A return to the main loop goes straight to the next macroinstruction’s handler, from the MACRO DISPATCH MEMORY.
THE 40-BIT WORDTHE TAG
40
bits a word, against 32
A tag in bits 39 to 32 over a 32-bit field, through every data path and in main memory.
GENERATIONSTHE PAGE TABLE
1
bit a page for the young generation’s pointers
A store of a pointer into the ephemeral space, of a type the pointer-type register names, sets its page’s ephemeral-reference bit in the page table. muir-sys’s generational collector reads those bits to scan only the pages that may point at young objects.
04 / HOW FAST
A clock a stage
and a cache.
The CADR takes a microcycle as a string of delay-line phases, 145 ns at its normal speed, and its memory board answers a request 458 ns later. QUUX has no delay lines: its pipeline runs at the period each board’s fit closes at, and a cache stands in front of memory.
Each board’s fit is routed and meets its period, and the board keeps the cache its block memory holds: the boards’ table gives both. A wrong prediction costs one bubble and a start that page-faults two: the pipeline, below.
05 / THE PIPELINE
Four stages,
one clock each.
Each microinstruction takes four stages of one clock each. Data moves left to right; control decisions flow back to the fetch. This is the design muir-sim’s rtl models and the FPGA core matches clock for clock.
The four stages are CS, fetch; RD, read and decide; EX, execute and check; and WB, write and start. Below the figure, six notes give what a wrong guess costs, why predictions pay, the fused dispatch D, the memory, halt and checkpoint, and the clock.
FIG. 03 — THE PIPELINEQUUX
What a wrong guess costs
A wrong prediction squashes the instructions behind the delay slot and restores RD’s copies: 1 bubble. A start that page-faults squashes late: 2 bubbles.
Why predictions pay
The profile pass sets each jump’s hint and each dispatch’s predicted target from the measured majority. Measured over the workloads, the hints save 2.7% of the clocks and the predicted targets 3.8%.
D, the fused dispatch
A main-loop return can fetch the next macroinstruction and dispatch on it. Its effects wait for the fetched word and start the handler in CS one clock later (L = 1). The microcode turns it on.
Memory
Two different caches sit on the way: the TLB holds address translations (a virtual page to a physical frame), and the data cache holds memory words. Writes are posted: WB hands them to the queue and goes on. A word written is fixed when its start’s microcycle ends. A read waits only when its line has a write still on its way.
Halt and checkpoint
A halt completes the instructions in EX and WB, squashes CS and RD, and waits for the port to empty. The machine then stands between two microcycles, as the single-edge simulator would.
The clock
QUUX runs on each board at the period its fit closes at, routed and met (the boards).
06 / ALL OF IT
Everything
QUUX changes.
The whole difference, the small parts with the large. Anything not named here is the CADR’s.
| Change | CADR | QUUX |
|---|---|---|
| The microinstruction | 48 bits. OA, functional destinations 16 and 17, is ORed into the next microinstruction by IMOD | Sixty-four bits: MIT’s 48 in IR<47:0>, meaning what they mean on the CADR, and an extension in IR<63:48>, read by the class: a conditional jump’s hint, a dispatch’s predicted target with its P and R, or an ALU or BYTE microinstruction’s PDL address field; an all-zero extension is the 48-bit microinstruction. Destinations 16 and 17 load OA-REG-LOW and OA-REG-HIGH, which keep their value until written again; a microinstruction takes one only through its OA select, SL IR<60> or SH IR<61>, which ORs it into nine fields. The control store and the boot PROM hold 64-bit instruction words, and WRITE-I-MEM writes IWR<63:32> from A<31:0> and IWR<31:0> from M<31:0> |
| Address translation | Five-bit level-1 map entries: 32 blocks of level-2 entries, 1,024 in all, block 37 the invalid one, so 31 regions of 8K words mapped at once; the microcode loads the map from its page hash table | No map. Virtual addresses are 32 bits: VA<31:28> 0000 to 1101 paged, 1110 the device window and 1111 the physical memory window, main memory at physical VA<27:0>. A paged address goes through a direct-mapped TLB, 4,096 entries; a miss walks a two-level page table in main memory, the directory’s first frame in register-page word 220, a directory entry by VA<31:20> and a page entry by VA<19:10>, over pages of 1024 words and 28-bit frames. The first reference through an entry sets its accessed bit and the first write its modified bit, and a store of a pointer of a type the pointer-type register names into the ephemeral space sets its ephemeral-reference bit, ORed into the table by the hardware. MAP(MD) reads the entry for MD’s address; a store to WRITE-MAP writes, invalidates or empties the TLB. LC is 34 bits, and jump condition 12 compares the fields unsigned |
| MACHINE-ID, functional source 16 | Unassigned: nothing drives the M bus, and it reads all ones (unverified on a real CADR) | One microinstruction, no bus cycle: the signature 0x5155 in bits 31:16, the hardware revision in 15:4, processor type 4 in 3:0, and 0 in 39:32 |
The feature page, 35777777400–35777777477 | Nothing answers: a read times out and sets the Unibus NXM bit | Read-only device registers, in the device window. Word 0 the MACHINE-ID; 1 0, no level-1 map; 2 the TLB’s entries, 4,096; 3 to 7 16,384 PDL words, 16,384 control-store words, 1,024 A-memory words, 4,096 dispatch words, and multiply and divide, 3; 10 the tick, timer 0, 1; 11 to 13 the main screen’s width and height, bits a pixel and words a line, and first address, 34000000000; 14 the microsecond clock, 1; 15 the optional devices, a bit each, 7: the real-time clock, the file device and the Ethernet device; 16 the number of interval timers, 3; 17 the MACRO DISPATCH MEMORY’s entries, 1,024; 20 to 24 the board’s name, up to 20 characters, 4 a word, which the herald prints; 25 the clock’s period, in half nanoseconds; the rest 0. Software reads source 16 first and the page only on QUUX |
| PDL buffer | 1K words, pointer and index 10 bits | 16K words of 40 bits, pointer and index 14 bits, read back whole in functional sources 2 and 3 |
The register page, 35777777400–35777777777 | Its registers are the I/O board’s and the bus interface’s, on the Unibus | The device window’s last page. Words 0 to 77 the feature page; 100 the interrupt status, a bit for each source: timer 0, the tick, timer 1, timer 2, block-disk, the keyboard, the mouse, the file device and the Ethernet device; 101 the error status, a write clearing it; 102 ERRSTOP; 103 the real-time clock; 104 reset devices; 110 to 115 the interval timers; 120 to 123 the keyboard and mouse; 160 to 171 the file device; 200 to 203 block-disk; 210 the video controller; 220 to 227 the memory system: the page table’s directory, the ephemeral-reference enable, the pointer-type register, a count of refused write-backs and a count of posted writes answered with an error; 240 to 257 the Ethernet device; the rest reserved. Every register reads <39:32> as 0 and ignores a write’s, and those that hold a physical address take 28 bits |
| Boot PROM | MIT’s version 9, over control store 0 until the microcode turns it off with PROMDISABLE. It stops copying A memory in when the PDL index wraps to 0, which a 10-bit index does after 2000 words | muir-sys’s, 1K words of 64 bits at control store 36000 of its own, read only and never overlaid, so there is nothing to turn off; the machine resets to 36000. It boots from block-disk, reading the GPT and the microcode partition, and saves nothing; it resets the devices and writes timer 0’s period. It reads the microcode’s self-describing file, whose first section names the machine it is for, and halts on a machine or a microcode not its own |
| Multiply and divide | A step per bit: MUS, DVS1, DVS and DVREM, ALU functions 40, 51, 41 and 45. Functions 42 and 43 are the 74S181’s own | MUL, 42: 32 multiply steps in one instruction. DIV, 43: the first divide step and 31 more. Each bit for bit the step sequence, on the 32-bit field, the result’s bits 39 to 32 being M’s; DIVIDE-LAST-STEP and DVREM stay separate |
| Clocks | No clock in the processor: the clock is the display’s vertical interrupt, and the microsecond clock and interval timer are on the I/O board, on the Unibus. Functional destinations 3 to 7 write only M; sources 15 and 17 read all ones | Source 15 the microseconds since power-on, 32 bits. Three identical interval timers on the register page, words 110 to 115: each on or off, periodic or one-shot, a period of 1 to 16,777,215 µs, and a flag ORed into the interrupt pending that jump conditions 5 and 6 test under its own enable. Timer 0 is the tick; no timer resets to a period, and the boot PROM writes timer 0’s 16,667 µs. Destination 3 is timer 0’s control, for the microcode that turns its tick on there; destination 4 writes only M and source 17 reads all ones, as on the CADR |
| Reset devices | PROG.UNIBUS.RESET resets the boards on the Unibus | Word 104: a write with <0> set resets every device — the interval timers, the file device, block-disk and the Ethernet device — and the boot PROM writes it before it reads the disk; PROG.UNIBUS.RESET drives nothing. |
| The fused return | Functional destinations 5 to 7 write only M | Destination 5 writes the MACRO-DISPATCH register: the main loop’s address, the A-memory address of A-LOCALP and the M-memory address of M-AP, the enable in <31> and D’s in <30>; destination 6 the index of the MACRO DISPATCH MEMORY, 1,024 entries, feature word 17; destination 7 the entry at the index: the handler’s address, N, P, R and an operand bit. A return to the main loop that needs no fetch, when the next halfword’s entry has R and P clear, goes to the entry’s address. One that needs a fetch is D’s: the pipeline dispatches on the fetched word itself, its handler entering CS a clock after the word arrives, 7 clocks from the return to the handler’s commit on a hit. The microcode fills the entries and sets both enables at RESET-MACHINE |
| Speed | SPEED1 and SPEED0 in the mode register choose the read tap, extra slow to fast. Reset leaves extra slow, 220 ns, until the microcode asks for normal, 145 ns | No speed bits: a write of bits 1 and 0 goes nowhere, and every microcycle is the same from the boot on |
| No delay lines | The read tap and a 60 ns restart: 145 ns at normal speed | A pipeline of four stages, one clock each: CS reads the control store, RD reads M and chooses the next address, EX runs the microinstruction and checks RD’s choices, WB writes A, M and the PDL buffer and grants the memory starts. The clock is the period each board’s fit closes at. Programs end as on micro, microinstruction for microinstruction; only the time changes |
| Main memory | Memory boards on the Xbus, 458 ns from the request to XACK, behind the bus interface | On the processor’s own memory port, off the bus: 32MW by default, packed at 5 bytes a word in DDR on a board. Writes are posted: a queue of 8 and 16 accepted writes in flight, answered in order, and a read waits only for the writes queued or in flight to its line |
| Memory cache | None | Always fitted, as large as each board’s block memory holds (the boards). Unified and write-through, main memory and the frame buffer, lines of 8 words, 2-way, the least recently used line going; a hit lands two clocks after its grant; a disk transfer clears the sets of the words it writes |
| The bus interface | The board between the processor and both buses: arbitration, the Unibus map and its buffers, the interrupt control and error status, the debug cable | None: main memory and the frame buffer are on the memory port, the devices’ registers reached through the processor’s register decode, and each register it had is on the register page or gone |
| Device registers | On the Xbus, 32 bits, shared with memory and the frame buffer; an address nothing answers times out after 4.25 to 5.1 µs | No bus: the processor’s register decode reaches every device register on the register page, never cached; an address nothing answers in the device window fails at once, reads 0 and sets the NXM bit in word 101. A register reads <39:32> as 0 |
| The Unibus and the I/O board | The Unibus, 16 bits, with the I/O board: keyboard, mouse, clocks, the serial port and the Chaosnet interface | None. The keyboard is a FIFO of 64 key words and the mouse its counts on the register page; the microsecond clock is in the processor and the interval timers on the register page; the network is the Ethernet device; the serial port is dropped |
| Real-time clock | None | Word 103 of the register page: whole seconds since 1970-01-01 00:00 UTC, unsigned, 32 bits, read only; the host’s time, kept current by the host. |
| File device | None: files come over the Chaosnet from a file server | Folders of the host served under one pathname host, FILES: commands and responses in two rings in main memory, the bytes moved by direct memory access, words 160 to 171 its registers; the rings and buffers at 28-bit physical addresses on an 8-word line, 4 data bytes a word |
| Network | The Chaosnet interface on the I/O board, and Chaosnet’s protocols in Lisp | The Ethernet device, words 240 to 257: transmit and receive rings in main memory, Ethernet frames moved by direct memory access; it fills in and checks the IPv4, TCP, UDP and ICMP checksums, takes IPv4 and ARP only, and counts what it drops; feature word 15 <2> says it is there and word 100 <8> is its interrupt. In Lisp, in a network process: ARP, IPv4 with one address, netmask and gateway and no fragments, ICMP echo and PING, and a TCP that answers connections, with the TELNET server on port 23 over it; names from the host table, with no DNS and no DHCP. Behind the device is a tap: in muir-sim a UNIX socket to a program that moves the Ethernet frames to and from a tap of the host’s, and on a board the Linux program quux-ethernet-device and a tap on the board’s Linux. QUUX’s address decides the tap’s link: an address in 169.254.x.y makes a host-only tap, through which QUUX reaches the host alone; any other makes a LAN tap, through which QUUX is a computer of the host’s LAN, the host answering ARP on the LAN for QUUX’s address, by proxy ARP, and forwarding between the LAN and the tap. No Chaosnet |
| Debugging | The console’s registers on the Unibus, and a debug cable from one machine’s bus interface to another’s: MIT’s CC | The console’s registers are the host’s port alone: muir-sim’s prompt and checkpoints, the FPGA board’s Linux. No debug cable |
| Display | The TV board: 768 by 963 at 24 words a line, a sync program, a color map and the vertical interrupt | The video controller, its memory the frame buffer, on the memory bus and cached, the display reading it from memory by direct memory access, one bit a pixel, at most 1920 by 1080 and the width a multiple of 32, the size each board’s bitstream fixes. The buffer is in the device window from 34000000000, 4 bytes a word. The system reads the size from feature words 11 to 13 at boot. One register, word 210 of the register page, the mode: bit 2 black-on-white; 211 to 217 reserved. No interrupt. It is quux’s only display |
| Disk | The disk controller: cylinder, head, sector and unit; ten commands; the drive’s seeks and rotation | Block-disk, QUUX’s only disk: the same registers and command list, the disk address a block number in <27:0>: a block is 1,024 bytes and an entry of the command list a page of 1024 words, moved packed, 5 blocks a page, or 4 bytes a word, 4 blocks a page, as command bit 12 chooses; read and write only; one pack, unit 0; 100 µs a block (unverified). The CADR’s controller is cadr’s alone |
| The disk file | MIT’s pack: the blocks one after another, the label in block 0 naming up to 18 partitions, with the drive’s geometry | A raw image, a fixed VHD or a dynamic VHD, of any size, with a GPT partition table, made and filled with standard tools. A partition’s GPT name is its four-character name, a space and a comment of up to 31 characters; the current microcode and band are attribute bits. No geometry, no pack name |
| Reading a RAM as it is written | The RAM’s output floats while written, and the answer is a race | QUUX’s definition: the dispatch word a dispatch writes reads as it was before the write, and MAP(MD) right after a map write reads the old entry |
| Microcode | MIT’s 323 | muir-sys’s 2xxx releases, assembled for the 64-bit microinstruction with its OA selects: they read source 16 at boot and halt on a machine they are not for; page through the page table; use MUL and DIV in MPY, DIV and BIDIV’s quotient; run the clocks, the register page, block-disk’s two transfers and the fused return’s entries and D; and run the generational collector’s young collections and its walk of the marked pages. MIT’s 323 does not run on QUUX |
| Lisp system | MIT’s System 100 | muir-sys’s 2xxx releases: PROCESSOR-TYPE-CODE 4, fixnums of 32 bits, addresses unsigned over the 32-bit space, the main screen sized from the feature page’s words 11 to 13, its devices on the register page, its partitions found by GPT and a PAGE partition of 128MW, and a generational collector. Its herald names what runs it from words 20 to 24: Machine Type QUUX on Kria KR260. No CADR system runs on QUUX |
| Engines | micro, rtl and chip | micro and rtl; the memory port’s timing and the cache on rtl alone. chip is the CADR’s boards, netlist for netlist, and --chip is cadr’s alone |
07 / RUNNING IT
In software,
and in fabric.
QUUX’s released system runs in muir-sim and on FPGA boards; each page says how. Either one needs microcode and a system written for it, from muir-sys: MIT’s own will not run on it.
08 / SOURCES
Where each drawing
came from.
The drawings are read from muir-sim’s description of QUUX and from muir-fpga’s fabric; section names are the manual’s headings. Addresses are octal. The pipeline and its notes are read from muir-sim’s description of the pipeline and from muir-fpga’s fits on the boards.
| Figure | Read from |
|---|---|
| the processor | the CADR’s processor, above, and muir-sim’s docs/quux.md: “How software tells the two apart”, “The 40-bit word”, “The PDL buffer”, “Multiply and divide”, “The clocks”, “QUUX drops the delay lines”, “The memory port and the device registers”, “The memory cache”, “Its boot PROM, in its own addresses”, “The register page”, and its sections on the page table behind a TLB, the 64-bit microinstruction and the pipeline; muir-sim’s src/machine.rs, src/tlb.rs and src/pipeline/; the headers of muir-fpga’s rtl/machine/quux15_core.sv, quux15_store.sv, quux15_mmu.sv and quux15_port.sv |
| the whole machine | muir-sim’s docs/quux.md, from “The memory port and the device registers” to “The keyboard and the mouse”, and its sections on the page table behind a TLB and the Ethernet device, and docs/manual.md for --main-memory-size; QUUX’s Ethernet contract for the network; muir-fpga’s quux15_devices.sv and quux15_input.sv headers, rtl/plumbing/cadr_display_out.sv, and its docs/fpgarc.md, docs/file-device.md, docs/terminal.md, docs/console.md and docs/linux.md |
| the pipeline | muir-sim’s docs/quux.md, “rtl is the pipeline”, and QUUX’s pipeline contract with its rulings; the boards’ periods, muir-fpga’s docs/fits.md and docs/timing.md |