muir↗CADR PRESERVED.
QUUX EVOLVED.

THE MACHINES · CADR, MIT’S LISP MACHINE

CADR

The CADR is a 32-bit microcoded processor built at the MIT Artificial Intelligence Laboratory around 1978, and published as AI Memo 528 in 1980.

It is the machine the Lisp Machine system was written for. The drawings below are read from MIT’s own files.

The processor ↓QUUX, the CADR evolvedRunning it
PROCESSOR  32-bit, microcoded
CONTROL    48 bits x 16K words
CYCLE      145 ns
BUSES      Xbus and Unibus
BUILT      about 30

01 / A LISP MACHINE

Built at MIT
to run Lisp.

A screen, a keyboard, a mouse and a network.
And the system on it all written in Lisp.

The CADR is a computer built at the MIT AI Lab to run Lisp. It was one person’s workstation: a screen, a keyboard, a mouse and a network, and the system on it — the windows, the editor, the network code — was all written in Lisp.

Tom Knight, David Moon, Jack Holloway and Guy Steele drew it in about 1978. MIT built about thirty of them, and the first Lisp Machines LMI and Symbolics sold were built on it.

MIT’s schematics, wire lists, microcode and software for it survive. muir-sim simulates it from them, and muir-fpga puts it in the fabric of FPGA boards.

02 / THE CAGE AND ITS TWO BUSES

The whole machine.

FIG. 02 — THE WHOLE MACHINETHE CADR
the machine, whole a backplane or a cage a bus a cable an interrupt, the SPY bus the processor’s backplane CADR board the data paths: A and M, the ALU and byte hardware, the pushdown buffer, Q, VMA, MD, the map ICMEM board the control store and the boot PROM, the clock, the PC history, the diagnostic registers 1AJ1-J11 20 MEM<31:12> 1BJ1-J12 20 MEM<11:0>, -PMA, parity 1CJ1-J09 20 -ADR<21:0>, -MEMRQ, -MEMACK, -LOADMD 3AJ1-J07 20 SPY<15:0>, -MEMGRANT, WRCYC, INT five 40-wire cables, alternating grounds: 92 signals, 48 of them driven from both ends 1AJ1-J08 12 MCLK7, EADR<3:0>, -DBREAD, -DBWRITE and on the same cable, -BOOT1 and three resets INT the SPY bus: a Unibus master reads the diagnostic registers the Unibus's BR lines 1AJ2, 12 signals the light panel ten error lamps, the run lamp, and the boot button the bus cage bus interface slot 11 it arbitrates both buses and passes both interrupts master of the SPY bus the Unibus map the NXM timer DBGOUT and DBGIN Xbus 32 bits, open collector, 22 address bits; transfers asynchronous, arbitration clocked by -XBUS.SYNC memory boards one board is 65,536 words of 32 bits four banks of 4116s, self-refreshing an address switch puts each at its slot disk controller four registers at 0o17377774 a bus master: it moves blocks itself and selects one of eight drives display board — the TV a frame buffer of 32,768 words at 0o17000000, and eight control words at 0o17377760 color TV a second display board, a LISPM TV strapped to the color address optional Unibus a PDP-11 Unibus, open collector: 16 data bits, 18 address bits I/O board 0o764000 - 0o764176 the keyboard and the mouse a microsecond clock, an interval timer and a sixty-cycle clock a 2651 for the serial port the Chaosnet interface, with two packet buffers of 256 words four interrupt vectors, on one chain: 0o260 0o264 0o270 0o274 an SPC slot any PDP-11 device, the bus being an ordinary Unibus Trident drives up to eight packs, behind the disk multiplexor the screen 768 by 963, one bit a pixel, 60.5 frames a second keyboard, mouse 24 bits a key; seven mouse lines an RS-232 line through an MC1488/9 the Chaosnet a cable to other machines the debug cable, 21 signals another CADR the debugger. MIT’s console program CC runs on it, and its DBGOUT drives this DBGIN
The processor is two boards of its own; everything else in the machine plugs into one of the two buses the bus interface arbitrates.

03 / CONTROL AND DATA PATHS

The processor.

FIG. 03 — THE PROCESSORTHE CADR
the CADR's processor 32 bits or more narrower dotted: an IR field, or a condition a board a line from a name comes from that part ICMEM board CADR board control store 16,384 words of 48 bits, writable boot PROM: 1,024 words over the bottom of the control store until PROMDISABLE OPCs the last 8 PCs, read as source 6 IR I<47:0>, the microinstruction; OA, destinations 16 and 17, OR'd into the next one 48 next PC the SPC's top, IR<25:12>, the dispatch memory, PC + 1; 0 on a trap; SPC<14> and NEEDFETCH: a main-loop return IR<25:12> IR<44:42> PC 14 bits +1 PC<13:0> 14 SPC stack 32 words of 19 bits, a 5-bit pointer return address L, destination 15 dispatch memory 2,048 words of 17 bits: a PC and N, P, R IR<22:12> rotated M, up to 7 bits A, misc function 2 IWR writes the control store at the PC WRITE 48 A<15:0> and M<31:0> jump condition M < A, M <= A, M = A, from the ALU; a bit of the rotated M; page fault, from the map; interrupt pending: INT, from the bus interface, and <27>; sequence break, <26>; always A memory 1,024 words of 32 bits IR<41:32> A bus 32 M memory 32 words, a copy of A's first 32 IR<31:26> functional sources the dispatch constant, SPC, PDL pointer and index, PDL buffer, OPCs, Q, VMA, MAP[MD], MD, LC PDL buffer 1,024 words of 32 bits; pointer and index, 10 bits each IR<30>, PWIDX M bus 32 ALU 32 bits: boolean, add, subtract, and the multiply and divide steps IR<8:3>, IR<2> rotator rotates M left by 0 to 31 IR<4:0>, or LC's when IR<11:10> = 3 Q 32 bits, for multiply and divide IR<1:0> masker a mask of any length and position merges the rotated M into A: load byte, deposit byte, selective deposit IR<9:5> output bus selector the masker, the ALU, the ALU shifted right, or left with Q<31> Q<31> IR<13:12> OB 32 IR<25:14> L OB, held for the write pulse L writes A, M and the PDL buffer one microcycle later; the next instruction reads it through the pass-around, and the PDL buffer has none. OB also writes the functional destinations: LC, INTERRUPT-CONTROL, VMA, MD, the PDL pointer and index, and OA LC 26 bits, the byte address of the next instruction unit; LC/4 to VMA on fetch INTERRUPT-CONTROL <26> sequence break, <27> interrupt enable, <28> bus reset, <29> byte mode <29> VMA 32 bits, 24 used the map from VMA starting a cycle, else from MD; level 1: 2,048 × 5 bits, by <23:13>; level 2: 1,024 × 24 bits; a 22-bit physical address and the access bits MD 32 bits 24 ADR<21:0>, 22 MEM<31:0>, 32 to the bus interface, over the cables
The control store, its boot PROM and the OPCs are on the ICMEM board, and everything else drawn here is on the CADR board. Every result goes out on the output bus and is written back one microcycle later. Left out: parity, the statistics counter, the SPC’s write-pass, the carry lookahead and the boot trap; the diagnostic registers are on the whole machine above, and the clock is the next drawing.

04 / ONE MICROCYCLE

The clock.

FIG. 04 — ONE MICROCYCLETHE CADR
one microcycle, 145 ns at normal speed read phase, 85 ns write phase, 60 ns -TPR0 TSE on -TPR60 -TPR60 off -TPW45 TSE off SELECT the read tap the write pulse -TPDONE fast 135 ns, normal 145, slow 160, extra slow 220; ILONG adds 40 ns to the read phase the clock can wait at the end of the read phase, and hang at the end of the write phase
The read phase is set by a tap of a delay line, so the machine has four speeds and the instruction can ask for a long one.

05 / WHAT THE PROCESSOR RUNS

The microinstruction.

FIG. 05 — THE MICROINSTRUCTIONTHE CADR
the microinstruction, 48 bits bit 47 bit 0 ALU 47 STAT 46 ILONG 45 OP 44:43 POPJ 42 A SOURCE 41:32 M SOURCE 31:26 DESTINATION 25:14 OBUS SEL 13:12 MISC FUNC 11:10 9 ALU FUNCTION 8:3 CY 2 Q CTL 1:0 JUMP 47 STAT 46 ILONG 45 OP 44:43 POPJ 42 A SOURCE 41:32 M SOURCE 31:26 JUMP ADDRESS 25:12 MISC FUNC 11:10 R 9 P 8 N 7 NG 6 0/1 5 ROTATE / COND 4:0 DISPATCH 47 STAT 46 ILONG 45 OP 44:43 POPJ 42 DISPATCH CONSTANT 41:32 M SOURCE 31:26 L-PC 25 LC HK 24 xx 23 DISPATCH ADDRESS 22:12 MISC FUNC 11:10 MAPBT 9:8 BYTE LENGTH 7:5 ROTATE 4:0 BYTE 47 STAT 46 ILONG 45 OP 44:43 POPJ 42 A SOURCE 41:32 M SOURCE 31:26 DESTINATION 25:14 BYTE FUNC 13:12 MISC FUNC 11:10 LENGTH - 1 9:5 ROTATE 4:0 a field is drawn to the room its name needs, not to its width in bits
A JUMP with both its R and P bits set is not a jump at all: it is how the microcode writes the control store.

06 / WHAT ITS MICROCODE INTERPRETS

The macroinstruction.

FIG. 06 — THE MACROINSTRUCTIONTHE CADR
the macroinstruction, 16 bits bit 15 bit 0 CLASS I DEST 15:14 OP 13:9 REGISTER 8:6 DELTA 5:0 CLASS II SUB-OPCODE 15:13 OP 12:9 REGISTER 8:6 DELTA 5:0 CLASS III SUB-OPCODE 15:13 OP 12:9 ADR 8:0 CLASS IV DEST 15:14 OP 13:9 ADR 8:0 a field is drawn to the room its name needs, not to its width in bits
The microcode dispatches on bits 13 to 9 whatever the class, so an opcode whose bit 13 is a sub-opcode bit takes two entries of that table.

07 / VIRTUAL TO PHYSICAL

The map.

FIG. 07 — THE MAPTHE CADR
the map, 24 virtual bits to 22 physical VMA, the virtual address VMA<23:13> 11 bits, the level-1 index VMA<12:8> 5 bits VMA<7:0> 8 bits: a page is 256 words, passed through level 1 2,048 entries of 5 bits asynchronous RAM its five bits are VMAP VMAP VMA<12:8> level 2 1,024 entries of 24 bits asynchronous too, so a lookup is one ripple the word the second level puts out access 23 write 22 not read by the map 21:14 the physical page 13:0 the physical address, 22 bits the page the map gave 21:8 the word within the page 7:0 bit 23 permits the access at all and bit 22 permits a write; a refusal reaches the microcode as a page fault
The refusal is what a page fault is, and a JUMP can test for it.

08 / THE ADDRESS SPACE

What is where.

FIG. 08 — WHAT IS WHERETHE CADR
the physical address space, 22 bits 0o0 0o10000000 0o17000000 0o17400000 0o17777777 main memory one 64K-word board to a slot, up to 60 of the 64; 32 boards is 2,097,152 words the slots with no board in them a cycle here is answered by nothing and times out as a nonexistent memory Xbus I/O space 131,072 words, two slots the Unibus 131,072 words, two slots, reached two Unibus words at a time in Xbus I/O space 0o17000000 the display’s frame buffer, 32,768 words 0o17377760 the display’s eight control words 0o17377770 four words that answer nothing at all 0o17377774 the disk controller’s four registers on the Unibus 0o764000 the I/O board, through 0o764176 0o766000 the bus interface, through 0o766176: the sixteen diagnostic registers, the interrupt and error status, the debug block, and the sixteen map registers 0o140000 the window those map registers translate drawn to equal heights: main memory is half the space, and the two I/O regions together a sixteenth of it Unibus addresses are byte addresses: a 32-bit word is two of them, the low half the lower
A Unibus master reaches Xbus memory through the window at the foot, because the Unibus address space is not big enough to name it.

09 / A TRIDENT PACK

The disk.

FIG. 09 — THE DISKTHE CADR
the disk a head one marked block of the seventeen on a track a Trident pack 815 cylinders 5 heads on a T-80, 19 on a T-300 17 blocks a track, and a track is about 20,160 bytes a T-300 formatted at 17 holds 263,245 blocks the disk address, one word: three bits of unit, eight drives to a controller unit 30:28 cylinder 27:16 head 15:8 block 7:0 the command list the command list pointer names a list in main memory. Each word is a channel command word: bits 23 to 8 are a physical page and bit 0 says another follows. So one START moves a run of blocks into a run of unrelated physical pages. what a block is, on the surface 53 bytes PREAMBLE, all ones 8 bytes VFO LOCK, all ones 1 byte SYNC, octal 177 32 bits HEADER, whose fields are below 32 bits HEADER ECC 20 bytes VFO RELOCK, all ones 1 byte SYNC, octal 177 1 byte PAD, octal 377 1,024 bytes DATA: one Lisp Machine page, 256 words 32 bits DATA ECC 44 bytes POSTAMBLE, all ones the header, compared with the address the controller was told to read next block 31:30 zero 29:28 cylinder 27:16 head 15:8 block 7:0 everything goes low-order bit first, and the controller’s bits are complemented from the ones the drive sees the four registers, at 0o17377774 reading and writing one address are two different registers register read written 0 status command 1 the last memory address the command list pointer 2 the disk address the disk address 3 a soft error’s burst and place START
A block is one Lisp Machine page, and the drive carries three words of its own beside it: a header, a checkword over the header, and a checkword over the data.

10 / THE SCREEN AND ITS FRAME BUFFER

The display.

FIG. 10 — THE DISPLAYTHE CADR
the display the screen, 768 by 963 one bit a pixel a line is 24 words of 32 bits, drawn here across the top the frame buffer 23,112 words: the picture the other 9,656 32,768 words at 0o17000000, and the picture is exactly what the software puts there the eight control words at 0o17377760 0 the mode register: two clock-mode bits, black-on-white, an interrupt enable 1 the sync program RAM’s data at the pointer 2 the pointer 3 the enable, over the vertical spacing 4-7 they answer the bus and do nothing the vertical interrupt Bit 4 of the mode register is a flip-flop of its own, set at the start of a frame. With the interrupt enable it drives the Xbus interrupt line, and that is the machine’s roughly-sixty-cycle clock: 64.7 hertz, 966 lines of 16.000 us, under the PROM’s sync program, and 60.5 hertz under CPT-SYNC2, which every boot loads. The microcode hangs mouse tracking and its scheduler on it.
The frame is the machine's only regular interrupt, and the microcode counts time by it.

11 / KEYBOARD, MOUSE AND CLOCKS

The I/O board.

FIG. 11 — THE I/O BOARDTHE CADR
the I/O board 0o764000 0o764100 0o764120 0o764140 0o764160 0o764176 the first four groups of eight go nowhere the keyboard and mouse the beep and the status register the clocks and a port with nothing wired the Chaosnet interface five registers, two buffers the serial port a Signetics 2651 a key is a position: the word is 24 bits reserved, all ones 23:19 the source ID 18:16 the information, by source 15:0 for the new keyboard, source 001: zero 15:9 up or down 8 zero 7 the key 6:0 Both pressing and releasing a key send a code, so the machine knows the state of every key. Shift, Control, Meta and the rest are keys at positions of their own, and all key-encoding is done in the central machine. the mouse: seven lines, and no coordinates Four quadrature lines and three switches come in. They are latched twice, eight microseconds apart, and compared: any difference sets MOUSE READY. Each axis counts twelve bits, and a step is counted only when exactly one line of a pair moved, so a fast mouse loses counts. the clocks 0o764120 a 32-bit microsecond counter off a 32 MHz crystal, latched 0o764124 written, an interval timer on a 16 us clock; read, a sixty-cycle clock counting mains cycles since power-on 0o764126 a port with nothing wired to it, which reads as ones the interrupts Four vectors on one grant chain, each a ready bit with its own enable: 0o260 the keyboard and mouse, which share one; 0o264 the serial port; 0o270 the Chaosnet; 0o274 the clock. With more than one pending the clock is named first, then the Chaosnet, then the serial port, then the keyboard.
The microsecond clock starts when the power comes on, and no Unibus reset stops it.

12 / LAMPS AND ONE BUTTON

The light panel.

FIG. 12 — THE LIGHT PANELTHE CADR
the light panel on connector 1AJ2, which the schematic marks “TO LIGHT PANEL” ten error lamps -APE -MPE -PDLPE -DPE -IPE -SPE -HIGHERR -MEMPE -V0PE -V1PE the run lamp -MACHRUN the button -BOOT2 -APE the A memory -MPE the M memory -PDLPE the pushdown buffer -SPE the microcode return stack -DPE the dispatch memory -IPE the control store -MEMPE main memory -V0PE, -V1PE the map, one lamp a level -HIGHERR the A memory’s address parity pins 3 to 14 of the connector; pins 15 to 22 are not connected and on the ICMEM board itself Five TIL309 digits, the PC in octal, and each decimal point is a lamp: TILT1 the parity errors, TILT0 gathered into two groups DPE the dispatch memory IPE the control store PROMENABLE the boot PROM is selected
The button is one wire grounded by a push button, and it is one of the three ways a CADR can be told to boot.

13 / ONE CADR DEBUGGING ANOTHER

The debug cable.

FIG. 13 — THE DEBUG CABLETHE CADR
the debug cable the debugger a CADR, running CC its own Unibus cycle into 0o766100 - 0o766137 is what goes out on the cable DBGOUT 4 wires: -DEBUG OUT REQ, DEBUG OUT WR, A<1:0> 16 wires: DBD<15:0>, and either end may drive them 1 wire back: DEBUG OUT ACK MIT’s debug cable, 21 wires the debuggee DBGIN a 74S139 makes four strobes out of the two address bits, and one of the four makes it a master on this machine’s Unibus the four strobes -DB NEED UB a cycle on the debuggee’s own Unibus at the address last latched -DB READ STATUS drives the debuggee’s error status onto the low byte of the data lines -DB ADR1 CLK clocks three bits into the modifier register, one of which boots the debuggee -DB ADR0 CLK clocks sixteen bits into the address latches Nothing here carries meaning by an edge alone: every wire is held for the whole of a request, and the latches take the data at the trailing edge of their strobe, which is when the request lifts. The bus interface’s timeout PROM gives an ordinary cycle 10 microseconds, and one across the cable 30.
Once a cycle can run on the debuggee's Unibus, everything on that bus is reachable, main memory included, through the debuggee's own Unibus map.

14 / FROM MIT’S CAD FILES

Seven netlists.

Each board as a netlist: every chip on it and every wire between them, read out of MIT’s own CAD files. They are what muir-sim’s chip engine simulates.

2,016parts.

Parts in a whole machine — one memory board on the Xbus and both TV boards, the SIMPLE TV and the color TV, and 7,224 with all thirty-two memory boards.

Not drawn by hand. Pulled out of MIT’s own CAD files, then held pin for pin to MIT’s wire list for the same board.

NETLISTBOARDPARTS
CADR.netlistProcessor and control store, two boards in the one file985
BUSINT.netlistBus interface176
CADRM.netlistMain memory, 64K words a board, 32 on the Xbus for 2M words168
CADRIO.netlistI/O board: keyboard, mouse, clocks, the serial port, and the Chaosnet interface, which is the other half of the same board173
CADRDC.netlistDisk controller171
SIMPLETV.netlistThe standard black-and-white TV, which is MIT’s word for the screen171
LISPMTV.netlistThe LISPM TV in its four-bit build, which replaced the SIMPLE TV in December 1980; strapped to the color address it is the color TV as well. The eight-bit build is not built172

And the eighth, the disk multiplexor’s, which is fitted only when a run asks for it.

15 / RUNNING IT

In software,
and in fabric.

muir-sim runs the CADR as cadr, on three engines down to every chip, and boots MIT’s System 100 on it: build and boot. muir-fpga puts it in the fabric of FPGA boards. Either one gets its files and the time from ozd, its associated machine, over the Chaosnet.

16 / SOURCES

Where each drawing
came from.

Each drawing above was read from the sources listed here. MIT’s files are named as muir-sim keeps them, under mit/. Numbers written with a leading 0o are octal, which is how MIT writes an address.

FigureRead from
the whole machineMIT’s busint.erface, xspec.text.3 and the three wire lists; muir-sim’s data/cables.txt; AI Memo 528 for the interrupts, the SPY bus and the Unibus’s address bits; muir-sim’s docs/machine.md for the color TV
the processorAI Memo 528; MIT’s two print sets, cadr.book and icmem.book, page by page, and cadr/ir.bits; muir-sim’s data/CADR.netlist for what crosses the backplane, and its src/rtl.rs and src/machine.rs
one microcycleAI Memo 528, and the CLOCK1 delay-line taps as muir-sim’s clock.rs has them
the microinstructionMIT’s cadr/ir.bits, and muir-sim’s isa.rs for the bit ranges
the macroinstructionMIT’s sys/ucadr/uc-parameters.lisp and uc-macrocode.lisp, sys/sys2/disass.lisp, sys/man/code.text
the mapAI Memo 528, muir-fpga’s docs/map.md, MIT’s VMEM schematics
the address spaceMIT’s sys/doc/unaddr.text, muir-sim’s busint.rs, muir-fpga’s cadr_xbus_decode.sv
the diskMIT’s sys/doc/disk.text, and muir-sim’s dm.rs for the multiplexor
the displayMIT’s cadrtv/lmtv.order and shwarm.lisp, muir-fpga’s docs/tv.md
the I/O boardmuir-fpga’s docs/io-board.md, MIT’s sys/io1/ukbd.lisp and cadrio schematics
the light panelMIT’s cadrwd/icmem3.wlr, connector 1AJ2 pin by pin; AI Memo 528
the debug cablemuir-fpga’s docs/debug-cable.md, MIT’s cadr/ir.bits and the DBGOUT and DBGIN schematics

The sources themselves, file by file, are listed in muir-fpga’s docs/cadr.md and muir-sim’s docs/sources.md.