muir↗CADR PRESERVED.
QUUX EVOLVED.

muir-fpga · Terasic · Agilex 5 E-series

DE25-Nano

QUUX and the CADR mapped onto one Altera Agilex 5 E-series, the A5EB013B.

The processing system: 2 × Arm Cortex-A76 and 2 × Cortex-A55, running Linux.

The CADR’s drawingQUUX’s drawingHow it bootsThe debug cableArty Z7-20Kria KR260The maker’s page ↗
FIG. 01 — DE25-NANO, CADRMUIR-FPGA
this project another project board component Altera Agilex 5 E-series · A5EB013BB23BE4SCS display output scans both screens out of DDR at the monitor’s rate, side by side, the color one over the first; to the ADV7513 F2SDRAM fabric masters, 64 bits, AXI4, one port shared by burst HDMI out display out of the fabric, 1280 × 1024 at 60 Hz FPGA fabric logic ALM 18,108 of 46,800 38.7% M20K 337.5 KB of 895 KB 37.7% worst setup +2.353 ns clock CLOCK1, CLOCK2 100 MHz, 10 ns a tick 15 ticks=150 ns ICMEM board control store: 16K × 48, 768 Kb CADR board datapath, sequencer, scratchpads, maps 12 wires clock, SPY control, resets 80 wires MEM<31:0>, SPY<15:0> 48 driven from both ends bus interface BUSINT arbitration, the NXM timeout, the address decode, -HANG, its registers, the map, the cable debug cable adapter the cable both ways, 8 pins registers at LWH2F + 0x1000 20 out 19 in Xbus, 32 bits Unibus, 16 bits, open collector Xbus to DDR main memory and the display’s buffer an AXI4 master disk controller four registers, the channel that walks a list in memory CADRDC an AXI4 master TV scan counters and the mode register SIMPLETV the buffer is in DDR Color TV second display board: 576 × 454 × 4 bits LISPMTV 0o17200000 I/O board keyboard, mouse, clocks, serial Chaosnet registers and buffers CADRIO the cable, not the protocol H2F HPS masters, AXI4 LWH2F HPS masters, AXI4 HPS — Arm Linux — Buildroot 2×Cortex-A76 up to 1.4 GHz 2×Cortex-A55 up to 1.25 GHz Linux SPL U-Boot terminal an RFB server: the screen, the keys and the mouse Chaosnet routing, and the cable to the net for other machines serial serial line on a TCP socket, as muir-sim does disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over LWH2F a Unibus master USB input the keyboard and mouse, onto the I/O board via the terminal muir-sim on the HPS, running CC debugger ozd the files, the time and the host table DDR controller MAC gigabit Ethernet SD host the card UART Linux’s console 1 GB LPDDR4 16 MB reserved for main memory, 1 MB for the display, 128 KB for disk packs — and Linux has the rest, 938,276 kB GPIO header Debug cable 2 out + 2 in Vcc open both sides KEY0 — BOOT KEY1 — RESET LEDR0 — MACHRUN LEDR1 — fabric clock LEDR2 — microcycles LEDR3 — disk activity LEDR4 — ERRHALT LEDR5 — PROMENABLE SW0 — NO AUTO BOOT USB host keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; Chaosnet reaches other machines; the serial line is a TCP socket microSD U-Boot, CADR bitstream, Linux, root filesystem, disk packs, a file each USB-Blaster III one USB-C socket, console and JTAG
FIG. 02 — DE25-NANO, QUUXMUIR-FPGA
this project another project board component Altera Agilex 5 E-series · A5EB013BB23BE4SCS display output scans the frame buffer out of DDR at the monitor’s rate; to the ADV7513 F2SDRAM fabric masters, 64 bits, AXI4, one port shared by burst HDMI out display out of the fabric, 1280 × 1024 at 60 Hz FPGA fabric logic ALM 35,496 of 46,800 75.8% M20K 405 KB of 895 KB 45.3% worst setup +1.395 ns clock quux15_de25 50 MHz in, I/O PLL, period 25 ns, a stage a clock processor 40-bit word, MUL and DIV, control store 16K words, PDL buffer 16K words the TLB 4,096 entries, a walk on a miss memory port a cycle goes to the memory bus, a device register or nowhere cache 16,384 words, two ways, write-through, lines of 8 words device cycles register page physical 1777777400-1777777777 the feature words, read only; the interrupt status, errors, three interval timers and the real-time clock console boot, halt, step, status the registers on LWH2F device registers memory master lines of 8 words in five 64-bit beats quux15_axi_master an AXI4 master block-disk four registers, 200 to 203; blocks to and from a pack quux15_block_walk the pack side, a master video controller one-bit frame buffer, 1280 × 1024, a mode quux15_devices the buffer is in DDR file device two rings in main memory; registers quux15_devices its host face on H2F keyboard and mouse a FIFO of 64 key words, the mouse’s counts, buttons quux15_input the cable, not the protocol Ethernet device two rings in main memory; registers quux16_ethernet its host face on H2F H2F HPS masters, AXI4 LWH2F HPS masters, AXI4 HPS — Arm Linux — Buildroot 2×Cortex-A76 up to 1.4 GHz 2×Cortex-A55 up to 1.25 GHz Linux SPL U-Boot Ethernet device frames between the rings and quux0, a host-only tap or a LAN tap terminal an RFB server: the screen, the keys and the mouse file device serves FILES and sets the clock, from the card disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over LWH2F the registers USB input the keyboard and mouse, onto the register page via the terminal DDR controller MAC gigabit Ethernet SD host the card UART Linux’s console 1 GB LPDDR4 QUUX’s areas: 32MW main memory, 1 MB display, 128 KB packs — and Linux has the rest, 670.875 MB KEY0 — unused KEY1 — RESET LEDR0 — running LEDR1 — fabric clock LEDR2 — microcycles LEDR3 — disk activity LEDR4 — ERRHALT LEDR5 — dark LEDR6 — memory port open SW0 — unused USB host keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; a LAN tap puts QUUX on the LAN microSD U-Boot, the bitstream, Linux, root filesystem, disk packs, a file each USB-Blaster III one USB-C socket, console and JTAG