muir↗CADR PRESERVED.
QUUX EVOLVED.

muir-fpga · AMD · Zynq UltraScale+

Kria KR260

QUUX and the CADR mapped onto one AMD Zynq UltraScale+ XCK26, on a Kria KR260.

The processing system: 4 × Arm Cortex-A53, running Linux.

The board’s own loader, in its flash, is left alone: it reads the microSD card, which it sees as a USB disk, or a server on the network, and loads Linux and then the bitstream from there.

The tick is 10 ns, from the carrier’s 25 MHz clock through a clock manager. Main memory is on the first high-performance port and every port is 128 bits wide. The two user LEDs carry the lamps: UF1 shows the microcycles, and UF2 the error halt, or a slow blink while the machine boots.

The CADR boots its system from its disk pack, as LISPM-1, at Chaosnet address 177201, with ozd on the board as its associated machine. A USB keyboard and mouse at the board reach the machine, and Ctrl-Alt-Del from that keyboard cold-boots it.

A monitor on the board’s DisplayPort, J6, shows the machine at 1920×1080, 60 Hz: the CADR’s main screen and its color TV side by side at 1:1, with equal margins. The color TV is on by default on this board. After an idle time the monitor sleeps, and a key at the board wakes it; that key is swallowed. The boot chord works with the monitor asleep. The link is brought up by cadr-displayport, a small program of this project’s, and two of its tables are AMD’s, under the MIT License.

QUUX runs here too, in the second drawing: the 40-bit word in a pipeline of four stages, one clock each. Its memory master is 64 bits wide and reaches the 128-bit port as narrow bursts. It boots muir-sys’s system from its own boot PROM, and its screen fills the monitor.

The CADR’s drawingQUUX’s drawingThe cable’s connectorHow it bootsThe debug cableArty Z7-20DE25-NanoThe maker’s page ↗
FIG. 01 — KRIA KR260, CADRMUIR-FPGA
this project another project board component AMD Zynq UltraScale+ · XCK26-SFVC784-2LV-C display output scans both screens out of DDR at the monitor’s rate, side by side at 1:1, with equal margins, and hands them to the DisplayPort controller S_AXI_HP3_FPD FPGA masters, 128 bits DisplayPort controller DisplayPort J6, 1.2a, 1920 × 1080 Programmable Logic LUTs 15,309 of 117,120 13.1% BRAM 184.5 KB of 648 KB 28.5% URAM 0 of 64 0.0% worst setup +1.987 ns adapters in the fabric meet every port at 128 bits clock CLOCK1, CLOCK2 25 MHz in, MMCM, 100 MHz, 10 ns a tick 15 ticks=150 ns ICMEM board control store: 16K × 48, 768 Kb CADR board datapath, sequencer, scratchpads, maps 12 wires clock, SPY control, resets 80 wires MEM<31:0>, SPY<15:0> 48 driven from both ends bus interface BUSINT arbitration, the NXM timeout, the address decode, -HANG, its registers, the map, the cable debug cable adapter the cable both ways, 8 pins registers at HPM1 + 0x1000 20 out 19 in Xbus, 32 bits Unibus, 16 bits, open collector Xbus to DDR main memory and the display’s buffer an AXI4 master disk controller four registers, the channel that walks a list in memory CADRDC an AXI4 master TV scan counters and the mode register SIMPLETV the buffer is in DDR Color TV second display board: 576 × 454 × 4 bits LISPMTV 0o17200000 I/O board keyboard, mouse, clocks, serial Chaosnet registers and buffers CADRIO the cable, not the protocol S_AXI_HP0_FPD FPGA masters, 128 bits S_AXI_HP2_FPD FPGA masters, 128 bits M_AXI_HPM0_FPD Arm masters, 128 bits, the faces in 32-bit lanes M_AXI_HPM1_FPD Arm masters, 128-bit PS — Arm Linux — Buildroot 4×Cortex-A53 up to 1.33 GHz Linux QSPI U-Boot terminal an RFB server: the screen, the keys and the mouse Chaosnet routing, and the cable to the net for other machines serial serial line on a TCP socket, as muir-sim does disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over HPM1 a Unibus master USB input the keyboard and mouse, onto the I/O board via the terminal muir-sim on Linux, running CC debugger ozd the files, the time and the host table DDR controller HP0 shares a port with the DisplayPort DMA MAC J10C, gigabit Ethernet USB 0 the card, as a USB disk UART Linux’s console 4 GB DDR4 16 MB reserved for main memory, 1 MB for the display, 128 KB for disk packs — and Linux has the rest, 3,990,556 kB PMOD1 Debug cable 2 out + 2 in Vcc open both sides UF1 — microcycles UF2 — error halt Fan driven on, low is on USB 1 keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; Chaosnet reaches other machines; the serial line is a TCP socket microSD, J11 boot.scr, bitstream, Linux, root filesystem, disk packs, a file each USB-UART / JTAG micro-USB socket, console and JTAG
FIG. 02 — KRIA KR260, QUUXMUIR-FPGA
this project another project board component AMD Zynq UltraScale+ · XCK26-SFVC784-2LV-C display output scans the frame buffer out of DDR at the monitor’s rate, and hands it to the DisplayPort controller S_AXI_HP3_FPD FPGA masters, 128 bits DisplayPort controller DisplayPort J6, 1.2a, 1920 × 1080 Programmable Logic LUTs 31,767 of 117,120 27.1% BRAM 195.75 KB of 648 KB 30.2% URAM 14 of 64 21.9% worst setup +2.144 ns adapters in the fabric meet every port at 128 bits clock quux15_kr260 25 MHz in, MMCM, period 25 ns, a stage a clock processor 40-bit word, MUL and DIV, control store 16K words, PDL buffer 16K words the TLB 4,096 entries, a walk on a miss memory port a cycle goes to the memory bus, a device register or nowhere cache 65,536 words, two ways, write-through, lines of 8 words device cycles register page physical 1777777400-1777777777 the feature words, read only; the interrupt status, errors, three interval timers and the real-time clock console boot, halt, step, status the registers on HPM1 device registers memory master lines of 8 words in five 64-bit beats quux15_axi_master on the 128-bit port block-disk four registers, 200 to 203; blocks to and from a pack quux15_block_walk the pack side, a master video controller one-bit frame buffer, a mode quux15_devices the buffer is in DDR file device two rings in main memory; registers quux15_devices its host face on HPM0 keyboard and mouse a FIFO of 64 key words, the mouse’s counts, buttons quux15_input the cable, not the protocol Ethernet device two rings in main memory; registers quux16_ethernet its host face on HPM0 S_AXI_HP0_FPD FPGA masters, 128 bits S_AXI_HP2_FPD FPGA masters, 128 bits M_AXI_HPM0_FPD Arm masters, 128 bits, the faces in 32-bit lanes M_AXI_HPM1_FPD Arm masters, 128-bit PS — Arm Linux — Buildroot 4×Cortex-A53 up to 1.33 GHz Linux QSPI U-Boot Ethernet device frames between the rings and quux0, a host-only tap or a LAN tap terminal an RFB server: the screen, the keys and the mouse file device serves FILES and sets the clock, from the card disk packs a drive is a file, its blocks staged into DDR console halt, step and inspect over HPM1 the registers USB input the keyboard and mouse, onto the register page via the terminal DDR controller HP0 shares a port with the DisplayPort DMA MAC J10C, gigabit Ethernet USB 0 the card, as a USB disk UART Linux’s console 4 GB DDR4 QUUX’s areas: 32MW main memory, 1 MB display, 128 KB packs — and Linux has the rest, 3,843,388 kB UF1 — microcycles UF2 — error halt Fan driven on, low is on USB 1 keyboard and mouse USB host port a keyboard and a mouse, plugged into the board gigabit Ethernet the terminal is a VNC client; a LAN tap puts QUUX on the LAN microSD, J11 boot.scr, bitstream, Linux, root filesystem, disk packs, a file each USB-UART / JTAG micro-USB socket, console and JTAG

THE DEBUG CABLE

The debug cable.

The board’s end of the cable is PMOD1, the first of its four Pmod headers. Its pins, and what has run on them, are on the debugging page.